The embodiments described herein generally relate to the manufacture of silicon wafers, and more particularly to a method for stripping an insulator from the edge of a semiconductor wafer.
Semiconductor wafers are generally prepared from a single crystal ingot (e.g., a silicon ingot) which is trimmed and ground to have one or more flats or notches for proper orientation of the wafer in subsequent procedures. The ingot is then sliced into individual wafers. An individual donor wafer is bonded to a handle wafer to form a bonded wafer pair. Either the donor wafer or the handle wafer or both may have an insulating layer (e.g., an oxide layer) deposited on them prior to bonding. Subsequent processes are performed upon the bonded wafer pair, whereby the majority of the thickness of the donor wafer is removed, leaving a thin layer of silicon atop a thin layer of insulator bonded to the upper surface of the handle wafer (i.e. a silicon-on-insulator or SOI wafer).
The layers transferred from the donor wafer to the handle wafer do not extend to the radial edges of the bonded wafer, and instead terminate between one and five millimeters inward from the edge of the bonded wafer. A narrow annulus of exposed handle wafer (i.e., a terrace region) is left around the periphery of the bonded wafer. If an insulating layer is deposited on the handle wafer prior to bonding, the terrace region will be covered by this insulating layer. Silicon dioxide (“oxide”) is a commonly used insulating layer. Other insulating layers may be used if the composition of an etchant used to remove the layers is modified.
During subsequent processes such as a high temperature, gas phase etching in an HCl-containing ambient atmosphere to smooth and thin the top silicon layer surface (i.e., an epi-smoothing process), or an epitaxial silicon deposition to thicken the top silicon layer (i.e., an epi-thickening process) the presence of the insulating layer in this terrace region is generally deleterious. In the case of epi-smoothing, the presence of the insulating layer affects the etch rate of the top silicon layer adjacent to the terrace region, leading to undesirable thickness variations in the top silicon layer near the wafer edge. In the case of epi-thickening, in addition to a disruption of the epi deposition rate adjacent to the terrace, small islands of polysilicon can nucleate and grow on the insulating layer in the terrace region and produce nodule defects that negatively impact subsequent use of the wafer or component produced therefrom. Accordingly, removal of the insulating layer in the narrow annulus dramatically reduces the top silicon layer thickness variation and likelihood of defects being formed in the annulus during subsequent operations.
Previous systems for removing or stripping the oxide from the annulus portion of the bonded wafer only permit a single wafer to be processed at a time in what is commonly referred to as a spin etcher. Spin etchers generally direct an etchant at the terrace region while spinning the bonded wafer. Accordingly, the removal of silicon oxide in a spin etcher is a time-consuming and expensive owing to the cost of operation of the spin etcher. Furthermore, only one wafer can be processed at a time in a spin etcher.
Thus, there remains an unfulfilled need for a wafer edge treatment method that addresses the disadvantages of current edge treatment operations and is suitable for use in wafer processing operations utilizing bonded wafers.